CS 333: Assignment #7

Explicity Parallel Programming

This project covers designing a circuit using an explicitly parallel language: VHDL.


  1. Create circuits that implement a two input and-gate and a two input or-gate. Write a test-bench for each circuit that tests all possible '0' and '1' inputs.
  2. Create a circuit that implements the function Y = A and (not B) or A and (not C), using port maps of your and and or gate from step 1. Write a test-bench for the circuit that tests all possible '0' and '1' inputs.
  3. Create a circuit that implements a T flip-flop with asynchronous reset. The inputs to the circuit should be reset, clock, and T. If reset is low ('0'), the output of the F/F should be 0. If reset is high ('1') and T is low ('0'), then the F/F/ should maintain its current value. If reset is high and T is high ('1'), then at the rising edge of the clock, the output should toggle its value. Write a testbench that demonstrates the functionality of your circuit.
  4. Create a counter using port maps and the T flip-flops from the prior step. Create a test-bench for the circuit. You can use this skeleton file as an example of how to create a clock
  5. Make a maximal linear feedback shift register of length 4 or more. Write a test-bench that shows that your LFSR creates a pseudo-random sequence of maximal length for the number of bits.



Make a wiki page for your assignment and email the professor a zip file with all of your vhdl code. Your wiki page should have the following elements.

When you have finished your writeup, please put the following label on the wiki page.