Project 3: Reaction Timer
Purpose: to start exploring sequential digital circuits.
The purpose of this project is to build a circuit that will test your reaction time. You will need a 7-segment display driver, a timer state machine, and a top-level graphic design file.
The circuit should work as follows. It begins in an idle state with two digits displaying zeros. When the user hits the start button, the circuit should light up a red LED and wait for a period of time. Then the circuit should display a green LED and start counting (approximate milliseconds), showing the count on the two digits. When the user hits the reaction button, the count should stop and freeze. If the user hits the reaction button before the green LED lights up, the counter should show FF and the system should go back to the idle state. When the user hits the start button, the digit display should be set back to zeros.
- Make a new subdirectory for your project. Copy your 7-segment driver file (bdf or vhd) to your new project directory.
Start Quartus and then create a new project. Call it reaction (you
are welcome to call it whatever you like, but I will refer to the
project and the top level file as reaction).
Open your 7-segment driver file, then select Project->Add to project. Then select File->Create/Update->Make symbol file.
Create a new VHDL file with an entity called timer and name the file
timer.vhd. Insert the Moore state machine template. The reaction
circuit should have a clock, a reset, a start input, and a react
input. It should have three outputs: one 8-bit std_logic_vector that
sends the time (in ~ms) and two std_logic flags that control the red
and green LEDs.
Set up the states as sIdle, sWait, and sCount. Your circuit should initially be in the Idle state. When the user hits the start button it should move to the Wait state, stay there for a while, and then move to the Count state. When the user hits the react button, the Count state should move back to the Idle state. If the user hits the react button while the system is in the wait state, then the counter should be set to all 1s and the system should go back to the Idle state.
In order to both wait and count, you need an internal counter. Create an internal signal of type unsigned with 28 bits. Put it between the architecture statement and the begin, along with the state signal declaration. You'll also need to add 'use ieee.numeric_std.all' to your header section.
signal count : unsigned (27 downto 0);
Set up the reset condition so it activates on a '0'. It should set the state to sIdle and set the count to all zeros (28 of them).
Set up the rest of the state machine. Use the count variable to both have the circuit wait a while and to count how long the user's reaction is. If you set count to what is effectively a large negative number and add one to it, you will eventually get to 0 (which is an easy test).
For the output, get rid of the second process statement in the
template. Replace it with a few simple conditional signal assignments.
- Assign '1' to the green LED when state is equal to sCount and otherwise '0'.
- Assign a '1' to the red LED when state is equal to sWait, otherwise '0'.
- Assign a string of 8 zeros to mstime when the state is sWait, otherwise assign it bits 23 downto 16 of the internal counter. You'll need to cast it to a std_logic_vector using the function std_logic_vector().
- Create a new bdf file to be the top level file for your project. Call it reaction.bdf. Within it, place two instances of your 7-segment driver and one instance of the timer. Set up appropriate inputs and outputs for the circuit. (As an extension, make your top level file a VHDL file and use component and port map statements to connect the various elements.)
- Compile your circuit, assign pins, and then test it out. Be prepared to demonstrate your circuit at the beginning of the next lab.
- Use a VHDL for your top level file and use component and port map statements to connect the hex driver and state machine circuits.
- Write a testbench VHDL program for your circuit and simulate it using ghdl. You can use the brighttest.vhd file as a template.
- Add a linear feedback shift register to generate random wait times. See wikipedia for a reasonable explanation.
- Add the ability to keep track of the shortest reaction time. Display the fastest reaction time on the other two digits, and enable the ability to clear it.
- Make it a game for two players, with two reaction buttons, and see who is faster.
- Be creative.
Create a wiki page with your writeup. For each task, write a short description of the task, in your own words.
- Include a picture of the state machine diagram for your reaction circuit.
- Include a picture/diagram of your top-level design.
- Include pictures of your simulations, if any.
- Describe the hardware testing you undertook to prove the circuit works.
- Include a description, and pictures, of any extensions.
- Please supply a list of people you worked with, including TAs, and professors. Include in that list anyone whose code you may have seen, such as those of friends who have taken the course in a previous semester.
Give your wiki page the label cs232f16project3.
Put your bdf/VHDL files in a folder called project3 in your CS232 private subdirectory on the Courses server.