Due: Friday, October 20, 2017, 9:00 am (start of the class)
Pentium IV Cache Design
Split level 1 cache design with a 16K (214) instruction cache and an 8K (213) data cache. The L1 data cache has 64 byte lines and uses a 4-way set associative design. The L1 instruction cache uses a direct mapped design also with 64 (26) byte lines.
The L2 cache is 256K (218) with a line size of 128 (27) bytes, and it uses an 8-way set associative design.
Please answer the following questions.
Given a 32-bit address, show the tag, set, and word fields for the L2 cache.
Given a 32-bit address, how many lines are in the L1 data cache? How many sets?
Given the 32-bit address 0xFF0110A8, which line of cache would it map to in the L1 instruction cache, given the above design?
Explain why it might make sense for the L1 instruction cache to be direct mapped while the L1 data cache is 4-way set associative.
If the hit rate for the L-1 cache is 70% and the hit rate for the L-2 cache is 80%, how often does the CPU have to go all the way to main memory to retrieve data? How much benefit does the L2 cache provide?
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