Weekly Lab ExercisesThe lab exercises will be posted here weekly. The work in lab will lead into and be part of the week's project. Labs will also count significantly towards participation. |
Lab Instructor Information
Prof. Bruce A. Maxwell Office hours: Knock |
Lab Exercise 1: Digital Logic Circuits
Lab Exercise 2: Digital Hardware
Lab Exercise 3: VHDL State Machines
Lab Exercise 4: Connecting Components in VHDL
Lab Exercise 5: Machine Language Design
Lab Exercise 6: Memory
Lab Exercise 7: CPU Design
Lab Exercise 8: Assembler
Lab Exercise 9: Final Project