Lab 2: Programming Hardware
The purpose of this lab is to get you working with larger, pre-built modules in Quartus and to begin programming the DE1 hardware boards.
This lab you will need to complete on your own. The following labs you may work with a partner.
Tasks
- Start Quartus. Follow the new project wizard and create a new directory for lab 2. Call your first project flash. This is the name of the project and the top level entity, but it will not be the only design file you create and use. You will be placing multiple design files into the same directory so you can include one or more designs into the top-level entity.
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Select File->New and create a new VHDL file. VHDL is a programming
language for specifying hardware configurations. Use the Edit->Insert
Template option to select the Unsigned Adder full design
template.
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Change unsigned_adder to boxdriver in both the entity and architecture
declarations. Thens ave the file as boxdriver.vhd.
Simplify the template so it has only a single input signal (delete input b). Then remove the generic block and make both the input and output be unsigned (3 downto 0). The inputs are now unsigned binary vectors with 4 bits, indexed from 3 down to 0, with index 3 being the most significant bit.
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Delete the addition line in the architecture block and then insert the
template for a conditional signal assignment using Edit->Insert
Template.
Make the receiving signal be the first bit of the result output signal: result(0). Make the right side assign a '1' to result when a is "0000", "0001", "0010", or "0011" and otherwise '0'. The expression should look like the following.
result(0) <= '1' when a = "0000" or a = "0001" or a = "0010" or a = "0011" else '0';
Do the same for the other three result outputs, but make each one a '1' for a different set of four counter values.
- Select Project->Add current file to add the VHDL file to the current project. Then select File->Create symbol file so that you can include the project in other project files. This may require you to fix any bugs in the code.
- Create a new BDF file. Add 2 input pins and 4 output pins to the design. Name the two input pins clock and reset. Name the four output pins HEX0[2], HEX0[3], HEX0[4], and HEX0[6].
- Add an lpm_counter device: megafunctions->arithmetic. Set up the clock to be 4-bits with a clock and asynchronous reset as the only inputs. After inserting it into your design, hook up the clock and reset signals from the input pins.
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Add the boxdriver symbol to the graphic design file. Hook the counter
outputs to the boxdriver inputs. Then hook the four boxdriver outputs
to the four output pins. The circuit should look like the diagram below.
Save the file as flash.bdf, add the project to the file and then compile the project.
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Simulate the project.
- Make the netlist
- Send it to modelsim
- vsim flash
- View the wave window, then set up the clock and reset inputs.
- Add the output pins to the wave window.
- run 1000ns
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Back in Quartus, go to Assignments->Pin Planner. We need to make sure
the input and output pins are connected intelligently when we download
the design to hardware.
You will want to have the DE1 User Manual handy when assigning pins.
Use the popup menus for each pin to set them to the desired values. Connect the clock to the 27MHz clock input. Connect the reset to a push button. Connect the four outputs to segments 2, 3, 4, and 6 of seven segment display 0.
- Use the Tools->Programmer to download your circuit to the board. Test it out.
When you have completed the lab assignment, go ahead and get started on the second project.