Lab 4: Connecting components in VHDL
The purpose of this lab is to get you working with multiple VHDL files and connecting them without using a BDF file.
- Start Quartus. Follow the new project wizard and create a new directory for lab 4. Call your project calc. This is the name of the project and the top level entity, but it will not be the only design file you create and use.
Select File->New and create a new VHDL file. Use the following as a
template for your file. We're
-- simple template library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity calc is port ( a : in unsigned (3 downto 0); b : in unsigned (3 downto 0); c : in std_logic_vector (1 downto 0); result : out unsigned (4 downto 0) ); end entity; architecture rtl of calc is begin end rtl;
Now create another VHDL file called alu.vhd. Use exactly the same
template as above, but change the entity name to alu in both the
entity and architecture statements. Change the parameter names to d,
e, f, and q.
Make a process statement in the architecture body that is sensitive to signals d, e, and f. Then make a case statement on f which has the cases "00", "01", "10", and others. Have case "00" assign to q the sum of d and e. Have case "01" assign to q the difference of d and e. Have case "10" assign to q the bitwise AND of d and e. Have case "11" assign to q the bitwise OR of d and e. Note that you will have to AND each bit individually and concatenate them back together, all in the same statement. Note that you'll need to pad the 4-bit numbers to convert them to 5-bit numbers.
Go back to the calc.vhd file. Use the following component declaration
template. Put it in the declaration section of the architecture.
component <entity> <port statement> end component;
Copy the port statement from alu.vhd into the component statement. Replace <entity> with alu.
In the body of your architecture, make an instance of the alu
component. To make an instance of another circuit--like adding a
component to a BDF diagram--you use the port map statement.
A port map statement needs a unique name, the name of the component,
then port map and the argument list. The code below is how you would
create one instance of the ALU.
alu1: alu port map( d => a, e => b, f => c, q => result );
In the argument list, the first symbol is the parameter name and the second symbol is the local variable you are connecting to it.
Compile your file and then open the simulator. Run vsim calc,
then set up the waveform. Select a and create a wave that is
a counter with the default values. Select b and create a
wave that is a counter that starts at 1111 and goes to 0000 in a
period of 25ps. Select c and create a wave with a period of
200ps. Add result and then run the simulator for
To make viewing easier, right click on the symbol name in the waveform window and select Radix->Decimal for the a, b, and result signals.
When you have completed the lab assignment, go ahead and get started on the current project.