Due: Friday, October 25, 2024, 11:00 am (start of the class)

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Pentium IV Cache Design

Split level 1 (L1) cache into two parts: a 16KB (2¹⁴) instruction cache and an 8KB (2¹³) data cache. The L1 data cache uses a 4-way set associative design, and each line has 64 bytes (2⁶). The L1 instruction cache uses a direct mapping design and each line has 64 bytes.

The L2 cache is 256KB (2¹⁸), and the line size is 128 bytes (2⁷). It uses an 8-way set associative design.

The addressable unit is 1 byte.

Please answer the following questions.

1. Given a 32-bit address, what is the size for the tag, set, and word fields for the L2 cache?

2. Given a 32-bit address, how many lines are in the L1 data cache? How many sets?

3. Given the 32-bit address 0xFF0110A8, which line of cache would it map to in the L1 instruction cache, given the above design? Hint: the address is given in a hexadecimal format. Each number in hexadecimal uses 4 bits in binary to represent. The given address has 8 hexadecimal numbers, which is consistent with the 32-bit address (4 * 8 = 32).

4. Explain why it might make sense for the L1 instruction cache to be direct mapped while the L1 data cache is 4-way set associative.

5. If the hit ratio for the L-1 cache is 70% and the hit ratio for the L-2 cache is 80%, how often does the CPU have to go all the way to main memory to retrieve data? How much benefit does the L2 cache provide?

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