Homework 8 | CS 232

Due: Wednesday, December 4, 2024, 11:00 am (start of the class)

Email Ying your homework. The email subject should follow this format CS232 Fall2024 HW8 -- Your Name.

Superscalar

Given the following code gragment, answer the questions.

I1: R2 + R1 —> R1
I2: R1 - R2 -> R2
I3: R3 + R4 —> R3
I4: R5 op R3 —> R4
I5: R5 + R6 —> R3
I6: R1 + R5 -> R1

What are the RAW, WAW, and WAR dependencies in the code?
Register renaming can address some of the dependencies. Rewrite the code using the notation R#(a), R#(b) to describe the renamed register for a given #. (e.g. R1(a), R1(b))
Assume the above set of instructions are on a processor with 2 identical ALUs, each instruction needs 1 clock cycle to execute. To fetch, decode, and write back an instruction, each stage need 1 clock cycle. The superscalar is capable of fetching and decoding 2 instructions in order and in pair at a time and has 2 instances of the write-back pipelining stage. Given out-of-order issue & out-of-order completion, with register renaming, show the optimal ordering of the instruction and determine the total number of clock cycles to completion. Suppose the window size is large enough to buffer all decoded instructions, and there is no ALU conflict among instructions.