CS 232: Lab 2

Lab 2: Programming Hardware

The purpose of this lab is to give you experience writing VHDL code and using the seven-segment displays on the board. There are four 7-segment displays on the DE0 board (User Manual). Each one consists of seven individual bars which can be used to create numbers or letters. In particular, we use them to display the hexadecimal numbers 0 through F, so we often refer to them as the hex displays.

In the lab, we will light up the four bottom segments in a pattern: one at a time will be unlit in a clockwise manner as shown in this recording of an animation (note that this is an old recording and shows widgets for the old boards, but that the main point, i.e. the 7-segment displays, is correct). The lights will be driven by a counter.

Tasks

• If you are using the boards (Preferred method), follow these instructions.

  + (more detail)

  1. Setup a New Project

     Start Quartus. Use the new project wizard to create a new directory for project 2 with a subdirectory for this lab, calling the subdirectory flash (so that means your directory name will be something like srtaylor/CS232/Project2/flash). Call your project flash. This is the name of the project and the top level entity, but it will not be the only design file you create for this project. You will be placing multiple design files into the same project and directory so you can include one or more designs into the top-level entity.

     During the project creation, set the Device to a Cyclone III and set the device name to EP3C16F484C6.

  2. Create a New VHDL File Using a Template

     The next step is to create a simple digital circuit with four inputs and four outputs. The four inputs will be from a counter and the four outputs will ultimately map to the seven-segment display. A high signal turns a segment off, and a low signal turns a segment on (YES, this is not a typo - it is the opposite of what you might expect). We want to unlight one segment at a time, so if we interpret the four binary inputs as a number, each output should be high ('1') for a sequence of four consecutive numbers (e.g. 0 to 3). We will make this circuit into a symbol to be used by the top-level design file, but it is not the top-level file itself (which means you shouldn't name it flash.vhd).

     Select File->New and create a new VHDL file. VHDL is a programming language for specifying hardware configurations. Use the Edit->Insert Template option to select the Unsigned Adder full design template.

     

  3. Customize the Template

     Change unsigned_adder to boxdriver in both the entity and architecture declarations. Then save the file as boxdriver.vhd.

     For all VHDL files, be sure to make the filename match the entity name.

     Simplify the template so it has only a single input signal (delete input b). Then remove the generic block and make both the input and output be std_logic_vector (3 downto 0). The inputs are now standard logic vectors with 4 bits, indexed from 3 down to 0, with index 3 being the most significant bit.

  4. Start Building the Circuit

     Delete the addition line in the architecture block and then insert the template for a conditional signal assignment using Edit->Insert Template.

     

     Make the receiving signal be the first bit of the result output signal: result(0). Make the right side assign a '1' to result when a is "0000", "0001", "0010", or "0011" and otherwise '0'. The expression should look like the following.

     result(0) <= '1' when a = "0000" or a = "0001" or a = "0010" or a = "0011" else '0';

     The above is called a conditional signal assignment. This statement is an asynchronous statement, which means it is running continuously, in parallel to any other statements in your program. Whenever the condition variable a on the right side changes, the value of the left side is updated.

     Do the same for the other three result outputs, but make each one a '1' for a different set of four consecutive counter values. So result(1) should be '1' when the input a is equal to 4, 5, 6, or 7 (binary).

  5. Add the File to the Project

     Select Project->Add current file to add the VHDL file to the current project. Then select File->Create symbol file so that you can include the project in other project files. This may require you to fix any bugs in the code. If you just want to check syntax on a VHDL file, select Processing->Analyze File.

  6. Simulate the Circuit

     Simulate the box driver file. Download this test bench file and take a look at it. Then use ghdl to compile it and your boxdriver.vhd file to make a waveform file.

     ghdl -a boxtest.vhd boxdriver.vhd
     ghdl -e boxtest
     ghdl -r boxtest --vcd=boxtest.vcd
     gtkwave boxtest.vcd &
     

     Take a look at the output and make sure you understand what it says about your circuit before continuing.

  7. Create the Top-Level Design File

     Create a new BDF file and save it as flash.bdf. Add 2 input pins and 4 output pins to the design. Name the two input pins clk and reset. Name the four output pins HEX0_2, HEX0_3, HEX0_4, and HEX0_6.

     Add an lpm_counter device: Under the Tools menu, go to the MegaWizard Plug-in Manager, megafunctions->arithmetic. Set up the clock to be 4-bits with a clock and asynchronous clear as the only inputs. After inserting it into your design, hook up the clock and aclr signals from the input pins (clk and reset).

     Add the boxdriver symbol to the graphic design file. Hook the counter outputs to the boxdriver inputs. Then hook the four boxdriver outputs to the four output pins. The circuit should look like the diagram below.

     

     Save the file again and add the file to the project. Then compile the project.

  8. Make Pin Assignments for the Board

     Back in Quartus, go to Assignments->Pin Planner. We need to make sure the input and output pins are connected intelligently when we download the design to hardware.

     You will want to have the DE0 User Manual handy when assigning pins.

     Use the popup menus (or just type the names) in the location field for each pin to set them to the desired values, or just type the pin name (e.g. PIN_R22) into the pin field. Connect the clock to the leftmost push button. Connect the reset to the rightmost switch. Connect the four outputs to the segments 2, 3, 4 and 6 in the rightmost seven-segment display.

  9. Program the Board

     Use the Tools->Programmer to download your circuit to the board. If the programmer says 'No Hardware', then select Hardware Setup and in the popup menu select USB blaster. Test out your circuit by holding down the reset push button (which is 0 when pressed) and then push the clock input.

• If you are not using the boards, follow these instructions.

  + (more detail)

  1. Setup a New Project

     Start Quartus. Use the new project wizard to create a new directory for project 2 with a subdirectory for this lab, calling the subdirectory flash (so that means your directory name will be something like srtaylor/CS232/Project2/flash). Call your project flash. This is the name of the project and the top level entity, but it will not be the only design file you create for this project. You will be placing multiple design files into the same project and directory so you can include one or more designs into the top-level entity.

     During the project creation, ignore the Device setup.

  2. Create a New VHDL File Using a Template

     The next step is to create a simple digital circuit with four inputs and four outputs. The four inputs will be from a counter and the four outputs will ultimately map to the seven-segment display. A high signal turns a segment off, and a low signal turns a segment on (YES, this is not a typo - it is the opposite of what you might expect). We want to unlight one segment at a time, so if we interpret the four binary inputs as a number, each output should be high ('1') for a sequence of four consecutive numbers (e.g. 0 to 3). We will make this circuit into a symbol to be used by the top-level design file, but it is not the top-level file itself (which means you shouldn't name it flash.vhd).

     Select File->New and create a new VHDL file. VHDL is a programming language for specifying hardware configurations. Use the Edit->Insert Template option to select the Unsigned Adder full design template.

     

  3. Customize the Template

     Change unsigned_adder to boxdriver in both the entity and architecture declarations. Then save the file as boxdriver.vhd.

     For all VHDL files, be sure to make the filename match the entity name.

     Simplify the template so it has only a single input signal (delete input b). Then remove the generic block and make both the input and output be std_logic_vector (3 downto 0). The inputs are now standard logic vectors with 4 bits, indexed from 3 down to 0, with index 3 being the most significant bit.

  4. Start Building the Circuit

     Delete the addition line in the architecture block and then insert the template for a conditional signal assignment using Edit->Insert Template.

     

     Make the receiving signal be the first bit of the result output signal: result(0). Make the right side assign a '1' to result when a is "0000", "0001", "0010", or "0011" and otherwise '0'. The expression should look like the following.

     result(0) <= '1' when a = "0000" or a = "0001" or a = "0010" or a = "0011" else '0';

     The above is called a conditional signal assignment. This statement is an asynchronous statement, which means it is running continuously, in parallel to any other statements in your program. Whenever the condition variable a on the right side changes, the value of the left side is updated.

     Do the same for the other three result outputs, but make each one a '1' for a different set of four consecutive counter values. So result(1) should be '1' when the input a is equal to 4, 5, 6, or 7 (binary).

  5. Add the File to the Project

     Select Project->Add current file to add the VHDL file to the current project. Then select File->Create symbol file so that you can include the project in other project files. This may require you to fix any bugs in the code. If you just want to check syntax on a VHDL file, select Processing->Analyze File.

  6. Simulate the Circuit

     Simulate the box driver file. Download this test bench file and take a look at it. Then use ghdl to compile it and your boxdriver.vhd file to make a waveform file.

     ghdl -a boxtest.vhd boxdriver.vhd
     ghdl -e boxtest
     ghdl -r boxtest --vcd=boxtest.vcd
     gtkwave boxtest.vcd &
     

     Take a look at the output and make sure you understand what it says. Draw the lit segments for at least one point in time to make sure it will appear as you intend it to.

When you have completed the lab assignment, go ahead and get started on the second project.