The lecture notes and homework assignments are posted here.

Week 1

Wednesday, 09/04

• Course Overview
• Overview of Computer Organization

Friday, 09/06

• Basic Concepts (I): Base 2 Integer Encoding, 2's Complement

Week 2

Monday, 09/09

• Boolean Algebra: Logical Operations, Truth Tables
• Circuits (I): Gates

Wednesday, 09/11

• Circuits (II): General Rule, Sum of Products, Create a Circuit Based on a Specification, K-map
• Homework 1

Friday, 09/13

• Homework 1 Discussion
• Basic Concepts (II): Octal and Hexadecimal
• Quiz 1

Week 3

Monday, 09/16

• Quiz 1 Discussion
• Circuits (III): Decoder

Wednesday, 09/18

• Circuits (IV): MUX, DEMUX
• Homework 2

Friday, 09/20

• Homework 2 Discussion
• VHDL (I): A half adder
• Quiz 2

Week 4

Monday, 09/23

• Quiz 2 Discussion
• VHDL (II): A full adder
• VHDL (III): A full adder in VHDL, Two-bit adder

Wednesday, 09/25

• VHDL (IV): Two-bit adder, Test the twoBitAdder using a counter
• Sequential Circuits (I): State machines, Moore machines
• Homework 3

Friday, 09/29

• Homework 3 Discussion
• Sequential Circuits (II): S-R Latch
• Quiz 3

Week 5

Monday, 09/30

• Quiz 3 Discussion
• Sequential Circuits (III): Clocked S-R Latch, Locked D Latch, Edge-triggered D Latch, Registers

Wednesday, 10/02

• Sequential Circuits (IV): ALU, ROM, PC, and IR

Friday, 10/04

• Programmable Circuits (I): A simple circuit -- Count

Week 6

Monday, 10/07

• Programmable Circuits (II): Extended Count

Wednesday, 10/09

• Programmable Circuits (III): A Loop for the Extended Count, IAS Computer
• Homework 4

Friday, 10/13

• Homework 4 Discussion
• Quiz 4

Week 7

Monday, 10/14

• Fall Break (No Class)

Wednesday, 10/16

• Quiz 4 Discussion
• Memory (I): Memory Categories, Capacity Units, Addressable Unit, Memory Hierarchy, Locality of Reference, Access Time

Friday, 10/18

• Memory (II): Cache Structure, Direct Mapping

Week 8

Monday, 10/21

• Memory (III): Direct Mapping (cont.), Associative Mapping, Set-associative Mapping

Wednesday, 10/23

• Memory (IV): Examples for Maaping Functions
• Homework 5

Friday, 10/25

• Homework 5 Discussion
• Quiz 5

Week 9

Monday, 10/28

• Quiz 5 Discussion
• Instruction Set Architecture (I): Stack Architecture, Accumulator Architecture, Register-Set Architecture

Wednesday, 10/30

• Instruction Set Architecture (II): Register-Register Architecture, Register-Memory Architecture, Memory-Memory Architecture, CISC vs RISC

Friday, 11/01

• Instruction Set Architecture (III): Types of Operations
• Project Workshop

Week 10

Monday, 11/04

• Instruction Set Architecture (IV): Addressing Modes -- Immediate, Direct, Indirect, Register Direct, and Register Indirect

Wednesday, 11/06

• Instruction Set Architecture (V): Addressing Modes (cont.) -- Displacement
• Homework 6

Friday, 11/08

• Homework 6 Discussion
• Instruction Set Architecture (VI): Real Instruction Formats
• Quiz 6

Week 11

Monday, 11/11

• Quiz 6 Discussion
• Pipelining (I): What is pipelining? Multi-stage vs Single-stage CPU

Wednesday, 11/13

• Pipelining (II): Pipelining Calculation
• Homework 7

Friday, 11/15

• Homework 7 Discussion
• Pipelining (III): Structural Hazards
• Quiz 7

Week 12

Monday, 11/18

• Quiz 7 Discussion
• Pipelining (IV): Data Hazards, Control Hazards
• Assembly Language

Wednesday, 11/20

• Assembly Language (cont.): Two-pass Assembler
• Superscalar (I): What is superscalar? Limitations of superscalar

Friday, 11/22

• Superscalar (II): Register Renaming, Instruction Issue Policy: In-order issue, in-order completion

Week 13

Monday, 11/25

• Thanksgiving Break

Wednesday, 11/27

• Thanksgiving Break

Frida2, 11/29

• Thanksgiving Break

Week 14

Monday, 12/02

• Superscalar (III): Instruction Issue Policy (cont.)
• Homework 8

Wednesday, 12/04

• Homework 8 Discussion
• Quiz 8

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